;/*****************************************************************************
; * @file:    startup_me32g030.s
; * @description: CMSIS Cortex-M0 Core Device Startup File 
; *           for the ME32G030 Device Series ARM CC compiler only
; * @version: V1.0
; * @date:    2020/08/08
; /*****************************************************************************

;// <h> Stack Configuration
;// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;// </h>

Stack_Size      EQU     0x00000200

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
__initial_sp


;// <h> Heap Configuration
;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;// </h>

Heap_Size       EQU     0x00000200

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit


                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset

                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors
                EXPORT  __Vectors_End
                EXPORT  __Vectors_Size

__Vectors       DCD     __initial_sp              	; Top of Stack
                DCD     Reset_Handler             	; Reset Handler
                DCD     NMI_Handler               	; NMI Handler
                DCD     HardFault_Handler         	; Hard Fault Handler
                DCD     0                         	; Reserved
                DCD     0                         	; Reserved
                DCD     0                         	; Reserved
                DCD     0                         	; Reserved
                DCD     0                         	; Reserved
                DCD     0                         	; Reserved
                DCD     0                         	; Reserved
                DCD     SVC_Handler               	; SVCall Handler
                DCD     0                         	; Reserved
                DCD     0                         	; Reserved
                DCD     PendSV_Handler            	; PendSV Handler
                DCD     SysTick_Handler           	; SysTick Handler
                ; External Interrupts
                DCD     WDT_IRQHandler         		; 16+0, Watchdog interrupt Handler
                DCD     BOD_IRQHandler       		; 16+1, Brown Out Detect(BOD) interrupt Handler
                DCD     PWMFAULT_IRQHandler    		; 16+2, PWM Fault interrupt Handler
				DCD     PA_IRQHandler               ; 16+3, Port A Interrupt Handler 
				DCD     PB_IRQHandler               ; 16+4, Port B Timer1 Interrupt Handler
				DCD     PC_IRQHandler               ; 16+5, Port C Timer6 Interrupt Handler
				DCD     DMA_IRQHandler              ; 16+6, DMA Interrupt Handler
				DCD     BTIM0_IRQHandler            ; 16+7, Basic timer 0 Interrupt Handler   
				DCD     BTIM1_IRQHandler            ; 16+8, Basic timer 1 Interrupt Handler    
				DCD     BTIM2_IRQHandler            ; 16+9, Basic timer 2  Interrupt Handler
				DCD     BTIM3_IRQHandler            ; 16+10, Basic timer 3  Interrupt Handler   
				DCD     CTIM0_IRQHandler            ; 16+11, Advance timer 0 Interrupt Handler
				DCD     CTIM1_IRQHandler            ; 16+12, Advance timer 1 Interrupt Handler
				DCD     ADC_IRQHandler              ; 16+13, ADC Interrupt Handler
				DCD     I2C0_IRQHandler             ; 16+14, I2C0 Interrupt Handler
				DCD     I2C1_IRQHandler             ; 16+15, I2C1 Interrupt Handler          
				DCD     SPI0_IRQHandler             ; 16+16, SPI0 Interrupt Handler           
				DCD     SPI1_IRQHandler             ; 16+17, SPI1 Interrupt Handler 
				DCD     PWM_IRQHandler         		; 16+18: PWM Interrupt Handler                
                DCD     UART0_IRQHandler          	; 16+19: UART0 Interrupt Handler
                DCD     UART1_IRQHandler           	; 16+20: UART1 Interrupt Handler             
                DCD     UART2_IRQHandler           	; 16+21: UART2 Interrupt Handler
                DCD     UART3_IRQHandler            ; 16+22: UART3 Interrupt Handler                
                DCD     ACMP0_IRQHandler            ; 16+23: Comparator 0 Interrupt Handler
                DCD     ACMP1_IRQHandler			; 16+24: Comparator 1 Interrupt Handler
                DCD     RTC_IRQHandler          	; 16+25: RTC alarm Interrupt Handler
                DCD     0          					; 16+26: Reserved
                DCD     0          					; 16+27: Reserved
                DCD     0							; 16+28: Reserved
                DCD     0            				; 16+29: Reserved
                DCD     0            				; 16+30: Reserved
                DCD     0            				; 16+31: Reserved   

__Vectors_End

__Vectors_Size         EQU     __Vectors_End - __Vectors
                AREA    |.text|, CODE, READONLY
 
; Reset Handler

Reset_Handler   PROC
                EXPORT  Reset_Handler             [WEAK]
                IMPORT  __main
                LDR     R0, =__main
                BX      R0
                ENDP

; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler     PROC
                EXPORT  NMI_Handler               [WEAK]
                B       .
                ENDP
HardFault_Handler    PROC
                EXPORT  HardFault_Handler         [WEAK]
                B       .
                ENDP
SVC_Handler     PROC
                EXPORT  SVC_Handler               [WEAK]
                B       .
                ENDP
PendSV_Handler  PROC
                EXPORT  PendSV_Handler            [WEAK]
                B       .
                ENDP
SysTick_Handler PROC
               EXPORT  SysTick_Handler            [WEAK]
                B       .
                ENDP
Default_Handler PROC
                EXPORT  NMI_Handler               	[WEAK]
				EXPORT  WDT_IRQHandler           	[WEAK]
				EXPORT  BOD_IRQHandler           	[WEAK]
                EXPORT  PWMFAULT_IRQHandler      	[WEAK]
                EXPORT  PA_IRQHandler      			[WEAK]
                EXPORT  PB_IRQHandler      			[WEAK]
                EXPORT  PC_IRQHandler      			[WEAK]
                EXPORT  DMA_IRQHandler          	[WEAK]
                EXPORT  BTIM0_IRQHandler          	[WEAK]
				EXPORT  BTIM1_IRQHandler           	[WEAK]
                EXPORT  BTIM2_IRQHandler            [WEAK]
                EXPORT  BTIM3_IRQHandler            [WEAK]
                EXPORT	CTIM0_IRQHandler          	[WEAK]
                EXPORT	CTIM1_IRQHandler          	[WEAK]
                EXPORT  ADC_IRQHandler          	[WEAK]
				EXPORT  I2C0_IRQHandler            	[WEAK]
                EXPORT  I2C1_IRQHandler            	[WEAK]
                EXPORT  SPI0_IRQHandler            	[WEAK]
				EXPORT  SPI1_IRQHandler            	[WEAK]
                EXPORT  PWM_IRQHandler      		[WEAK]
                EXPORT  UART0_IRQHandler      		[WEAK]
                EXPORT  UART1_IRQHandler      		[WEAK]
                EXPORT  UART2_IRQHandler      		[WEAK]
                EXPORT  UART3_IRQHandler      		[WEAK]
                EXPORT  ACMP0_IRQHandler      		[WEAK]
                EXPORT  ACMP1_IRQHandler      		[WEAK]	
                EXPORT  RTC_IRQHandler				[WEAK]			
					
WDT_IRQHandler  
BOD_IRQHandler     
PWMFAULT_IRQHandler 
PA_IRQHandler   
PB_IRQHandler    
PC_IRQHandler
DMA_IRQHandler      
BTIM0_IRQHandler    
BTIM1_IRQHandler    
BTIM2_IRQHandler   
BTIM3_IRQHandler 
CTIM0_IRQHandler   
CTIM1_IRQHandler  
ADC_IRQHandler   
I2C0_IRQHandler   
I2C1_IRQHandler   
SPI0_IRQHandler   
SPI1_IRQHandler   
PWM_IRQHandler   
UART0_IRQHandler  
UART1_IRQHandler  
UART2_IRQHandler  
UART3_IRQHandler  
ACMP0_IRQHandler  
ACMP1_IRQHandler
RTC_IRQHandler

				B   .   
				ENDP

                ALIGN
  
; User Initial Stack & Heap

                IF      :DEF:__MICROLIB

                EXPORT  __initial_sp
                EXPORT  __heap_base
                EXPORT  __heap_limit

                ELSE

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + Stack_Size)
                LDR     R2, = (Heap_Mem +  Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR

                ALIGN

                ENDIF

                END

